4bit Ripple Carry Adder Block Diagram

Code:

module fourBitRippleCarryAdder(s,c4, A, B, Cin);
 input [3:0] A, B;
 input Cin;
 output [3:0] s;
 wire [2:0] cout;
 output c4;
 
 oneBitAdder Add1 (s[0],cout[0],A[0],B[0],Cin);
 oneBitAdder Add2 (s[1],cout[1],A[1],B[1],cout[0]);
 oneBitAdder Add3 (s[2],cout[2],A[2],B[2],cout[1]);
 oneBitAdder Add4 (s[3],c4,A[3],B[3],cout[2]);
 
endmodule

module oneBitAdder(s_out, c_out, l,m,n);
input l,m,n;
output s_out, c_out;
sumModule s1 (s_out, l,m,n);
carryModule c1 (c_out,l,m,n);
endmodule

module sumModule(sumOut, x,y,c_in);
input x,y,c_in;
output sumOut;
wire t;
xor x1 (t,x,y);
xor x2 (sumOut,t, c_in);
endmodule


module carryModule(carr_out, A, B, Cin);
output carr_out;
input A, B, Cin;
wire t1, t2, t3;
and a1 (t1,A,B);
and a2 (t2,B,Cin);
and a3 (t3,A,Cin);
or o1 (carr_out, t1, t2, t3);
endmodule

Testbench:

module fourBitRippleCarryAdderTb;
reg [3:0] ta,tb; 
reg tc;
wire [3:0] tsum; 
wire tcr;
  fourBitRippleCarryAdder DUT (.s(tsum), .c4(tcr),.A(ta), .B(tb), .Cin(tc));
initial
begin
#0 ta=4'b0000; tb=4'b0000; tc=1'b1;
#1 ta=4'b1110; tb=4'b0111; tc=1'b1;
#2 ta=4'b0011; tb=4'b0111; tc=1'b1;
#3 ta=4'b1100; tb=4'b1100; tc=1'b0;
#4 ta=4'b0101; tb=4'b0101; tc=1'b1;
#5 ta=4'b1101; tb=4'b0111; tc=1'b0;
#6 ta=4'b0001; tb=4'b0011; tc=1'b1;
#7 ta=4'b1111; tb=4'b1001; tc=1'b1;
#8 ta=4'b1011; tb=4'b1110; tc=1'b0;
#9 ta=4'b0011; tb=4'b1100; tc=1'b0;
end

initial
begin
  $monitor ($time, " ta=%d, tb=%d, tc=%d, tsum=%d, tcr=%d",ta,tb,tc,tsum,tcr);
end
  
  initial 
    begin
      $dumpfile("fourBitRippleCarryAdderTb.vcd"); 
      $dumpvars;
    end
  
endmodule

Ouput:

00 ta= 0, tb= 0, tc=1, tsum= 1, tcr=0
01 ta=14, tb= 7, tc=1, tsum= 6, tcr=1
03 ta= 3, tb= 7, tc=1, tsum=11, tcr=0
06 ta=12, tb=12, tc=0, tsum= 8, tcr=1
10 ta= 5, tb= 5, tc=1, tsum=11, tcr=0
15 ta=13, tb= 7, tc=0, tsum= 4, tcr=1
21 ta= 1, tb= 3, tc=1, tsum= 5, tcr=0
28 ta=15, tb= 9, tc=1, tsum= 9, tcr=1
36 ta=11, tb=14, tc=0, tsum= 9, tcr=1
45 ta= 3, tb=12, tc=0, tsum=15, tcr=0

Simulation: