4×1 Multiplexer Modeling Using Verilog With Testbench

Introduction

A multiplexer (MUX) is a fundamental digital circuit that selects one of several input signals and forwards it to a single output line based on a set of select lines. A 4×1 multiplexer, specifically, chooses one of four input signals using two select lines. This article explores the design and implementation of a 4×1 multiplexer using Verilog, a hardware description language (HDL) widely used for modeling and verifying digital systems.

By constructing a 4×1 multiplexer from smaller 2×1 multiplexers, we demonstrate Verilog’s structural modeling approach, which emphasizes modularity and reusability. This tutorial provides a comprehensive guide to the design, including a testbench for verification and output analysis to confirm functionality. Understanding multiplexers is essential for designing complex digital systems, and this article equips readers with the skills to model and verify such circuits using Verilog.

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Background

A 4×1 multiplexer has four input lines (often labeled I0, I1, I2, I3), two select lines (S[1:0]), and one output line (Y). The select lines determine which input is routed to the output according to the following logic:

• S = 00: Selects I0
• S = 01: Selects I1
• S = 10: Selects I2
• S = 11: Selects I3

Mathematically, the output of a 4×1 multiplexer can be expressed as:

In this design, the 4×1 multiplexer is implemented using two 2×1 multiplexers, showcasing a hierarchical approach that simplifies the design process. This modular structure is particularly effective in Verilog, allowing for scalable and maintainable code.

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4×1 Multiplexer Block Diagram

The block diagram of a 4×1 multiplexer illustrates its four inputs, two select lines, and single output. It provides a high-level view of the circuit’s functionality, highlighting the selection mechanism driven by the select lines.

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4×1 Multiplexer Using 2×1 Multiplexers

To implement a 4×1 multiplexer, we can use a hierarchical approach by combining smaller 2×1 multiplexers. A 2×1 multiplexer selects one of two inputs based on a single select line. By cascading two 2×1 multiplexers, we can achieve the functionality of a 4×1 multiplexer. The diagram below shows how two 2×1 multiplexers are connected to form a 4×1 multiplexer, with intermediate signals facilitating the selection process.

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Truth Table

The truth table for a 4×1 multiplexer defines its behavior by mapping the select lines to the selected input. For simplicity, we assume inputs I0, I1, I2, I3 are provided, and the output Y reflects the selected input.

S1	S0	Selected Input	Output (Y)
0	0	I0	I0
0	1	I1	I1
1	0	I2	I2
1	1	I3	I3

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Verilog Modeling of 4×1 Multiplexer

The 4×1 multiplexer is modeled using Verilog’s structural and behavioral modeling approaches. The design is implemented hierarchically, with a 4×1 multiplexer module composed of two 2×1 multiplexer modules. The 2×1 multiplexer uses behavioral modeling for flexibility, while the 4×1 multiplexer employs structural modeling to demonstrate modularity.

2×1 Multiplexer Module

The 2×1 multiplexer module uses behavioral modeling to select between two inputs based on a single select line.

module twoRatioOneMux(Y0, S0, A0, B0);
    input A0, B0, S0;
    output reg Y0;
    always @(S0, A0, B0)
    begin
        if (S0 == 0)
            Y0 <= A0;
        else
            Y0 <= B0;
    end
endmodule
    

The module takes two inputs (A0, B0) and a select line (S0), producing output Y0. The always block triggers on changes to S0, A0, or B0, assigning A0 to Y0 when S0 = 0 and B0 when S0 = 1.

4x1 Multiplexer Module

The 4x1 multiplexer module is built structurally by instantiating two 2x1 multiplexers.

module fourRatioOneMux(Y, S, A, B);
    input A, B;
    input [1:0] S;
    output Y;
    wire t1, t2;
    twoRatioOneMux M1(t1, S[0], A, B);
    twoRatioOneMux M2(Y, S[1], t1, t1);
endmodule
    

The module takes two inputs (A, B) and a two-bit select line (S), producing output Y. The first 2x1 multiplexer (M1) selects between A and B based on S[0], producing intermediate signal t1. The second 2x1 multiplexer (M2) selects t1 based on S[1], producing the final output Y.

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Testbench for Verification

The testbench verifies the 4x1 multiplexer’s functionality by applying various input combinations and select line values, monitoring the output to ensure correct selection.

module fourRatioOneMuxTb;
    reg tA, tB;
    reg [1:0] tS;
    wire tY;
    fourRatioOneMux DUT(.A(tA), .B(tB), .S(tS), .Y(tY));
    initial
    begin
        #0 tA = 1'b0; tB = 1'b0; tS = 2'b00;
        #10 tA = 1'b0; tB = 1'b1; tS = 2'b01;
        #20 tA = 1'b1; tB = 1'b0; tS = 2'b10;
        #30 tA = 1'b1; tB = 1'b1; tS = 2'b11;
    end
    initial
    begin
        $monitor("input=%b%b selectorLine=%b Output=%b", tA, tB, tS, tY);
    end
endmodule
    

The testbench initializes inputs tA, tB, and select lines tS, applying four test cases with delays of 10ns between changes. The $monitor statement logs the inputs, select lines, and output tY. Note that the testbench does not include $dumpfile or $dumpvars, so waveform generation is not enabled.

Output:

input=00 selectorLine=00 Output=0
input=01 selectorLine=01 Output=1
input=10 selectorLine=10 Output=1
input=11 selectorLine=11 Output=1
    

The output reflects the multiplexer’s behavior, though the limited inputs (A, B) and select line configurations suggest a simplified design. A complete 4x1 multiplexer would require testing with four distinct inputs.

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Applications of Multiplexers

Multiplexers are versatile components in digital systems, with applications including:

• Data Routing: Directing data from multiple sources to a single destination in processors and communication systems.
• Signal Selection: Choosing between multiple input signals in control units and data buses.
• Memory Addressing: Selecting memory locations in RAM and ROM designs.
• Logic Function Implementation: Realizing combinational logic functions using multiplexers as lookup tables.
• Digital Signal Processing: Managing multiple data streams in DSP applications.

The 4x1 multiplexer’s ability to handle multiple inputs makes it a critical component in scalable digital designs, from simple circuits to complex ASICs and FPGAs.

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Enhancements and Considerations

The provided design is functional but can be enhanced for broader applicability:

• Full 4x1 Multiplexer: Modify the design to include four distinct inputs (I0 to I3) for complete functionality.
• Data Flow Modeling: Implement the 4x1 multiplexer using a single assign statement to express the Boolean equation directly.
• Waveform Generation: Add $dumpfile and $dumpvars to the testbench for simulation waveform analysis.
• Timing Analysis: Incorporate delay models to simulate real-world propagation delays.
• Scalability: Extend the design to support larger multiplexers (e.g., 8x1 or 16x1) using similar hierarchical techniques.

These enhancements can improve the design’s robustness and prepare it for integration into larger digital systems.

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Conclusion

Modeling a 4x1 multiplexer in Verilog using a hierarchical approach demonstrates the power of structural and behavioral modeling in creating modular digital designs. By composing the 4x1 multiplexer from 2x1 multiplexers, the design achieves clarity and reusability. The testbench verifies the circuit’s functionality, though a complete 4x1 multiplexer would require four inputs. Multiplexers are essential for data selection and routing in digital systems, and mastering their design in Verilog equips engineers with critical skills for building complex circuits. Verilog’s flexibility and simulation capabilities make it an invaluable tool for modern digital design.