XOR Logic Gate Modeling Using NAND Gates In Verilog

`timescale 1ns / 1ps

module xorUsingNand(output z, input x,y);
  wire w1,w2,w3;
  
  nand (w1,x,y);
  nand (w2,x,w1);
  nand (w3,y,w1);
  nand (z,w2,w3);
endmodule

module xorUsingNandTB();
  reg tx,ty;
  wire tz;
  
  xorUsingNand DUT(.z(tz),.x(tx),.y(ty));
  initial
    begin
      	 tx=0;ty=0;
      #2 tx=0;ty=1;
      #2 tx=1;ty=0;
      #2 tx=1;ty=1;
      #2 $finish;
    end
  
   initial
    begin
      $monitor ($time, " tx=%d, ty=%d, tz=%d",tx,ty,tz);
    end
  
  initial 
    begin
      $dumpfile("xorUsingNandTB.vcd"); 
      $dumpvars;
    end
endmodule

0 tx=0, ty=0, tz=0
2 tx=0, ty=1, tz=1
4 tx=1, ty=0, tz=1
6 tx=1, ty=1, tz=0