NOT Logic Gate Modeling Using Verilog

by

NOT GATE CIRCUIT:

NOT-GATE-CIRCUIT-DIAGRAM

TRUTH TABLE:

X Output(Z)
0 1
1 0

 

XNOR GATE MODELLING METHODS:

Data Flow Modelling:

`timescale 1ns / 1ps

module notGate(output z, input x);
  assign z= ~(x); 
endmodule

 

Behavioral Modeling:

`timescale 1ns / 1ps

module notGate(output reg z, input x);
  always @(x) 
    begin
      if ((x == 1'b0) 
        begin
          z = 1'b1;
        end
      else
        z = 1'b0;
    end
endmodule

 

Gate Level Modelling:

`timescale 1ns / 1ps

module notGate(output z, input x);
  not(z, x); 
endmodule

 

TESTBENCH:

`timescale 1ns / 1ps

module notGateTB();
  reg tx;
  wire tz;
  
  notGate DUT(.z(tz),.x(tx));
  
  initial
    begin
         tx=0;
      #2 tx=1;
      #2 $finish;
    end
  
  initial
    begin
      $monitor ($time, " tx=%d, tz=%d",tx,tz);
    end
  
  initial 
    begin
      $dumpfile("notGateTB.vcd"); 
      $dumpvars;
    end
  
endmodule

Output:

0 tx=0, tz=1
2 tx=1, tz=0

 

SIMULATION RESULTS:

Not-Gate-Simulation-Output

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