Two Bit Comparator Using Verilog With Testbench

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Two-Bit-Comparator-Block-Diagram

 

Truth Table:

A1 A0 B1 B0 X(A=B) Y(A>B) Y(A<B)
0  0  0  0  1  0 0 
0  0  0  1  0  0  1 
0  0  1  0  0  0  1 
0  0  1  1  0  0  1 
0  1  0  0  0  1  0 
0  1  0  1  1  0  0 
0  1  1  0  0  0  1 
0  1  1  1  0  0  1 
1  0  0  0  0  1  0 
1  0  0  1  0  1  0 
1  0  1  0  1  0  0
1  0  1  1  0  0  1 
1  1  0  0  0  1  0 
1  1  0  1  0  1  0 
1  1  1  0  0  1  0 
1  1  1  1  1 0  0 

 

Boolean Expression:

X = (A1 XNOR B1).(A0 XNOR B0)
Y = A1(B1') + (A1 XNOR B1).(A0.(B0'))
Z = (A1')(B1) + (A1 XNOR B1).(A0').B0))

 

 

CODE:

module twoBitComparator(tbc_eq, tbc_lt, tbc_gt, A, B);
  input[1:0] A, B;
  output tbc_lt, tbc_gt, tbc_eq;
  wire lt1, gt1, eq1,lt2, gt2, eq2,t1,t2,t3;
  
  oneBitComparator c1(lt1, gt1, eq1, A[0], B[0]);
  oneBitComparator c2(lt2, gt2, eq2, A[1], B[1]);
  
  and andmain1(tbc_eq,eq1,eq2);
  
  and andmain3(t2,eq2,gt1);
  or ormain2(tbc_gt,t2,gt2);
  
  and andmain2(t1,eq2,lt1);
  or ormain1(tbc_lt,t1,lt2);
endmodule

module oneBitComparator(lt, gt, eq, A, B);
  input A, B;
  output lt, gt, eq;
  lt l1(lt, A, B);
  gt g1(gt, A, B);
  eq e1(eq, A, B);
endmodule

module lt(lt_out, lt_a, lt_b);
  input lt_a, lt_b;
  output lt_out;
  wire temp;
  not n1(temp,lt_b);
  and a1(lt_out, lt_a, temp);
endmodule

module gt(gt_out, gt_a, gt_b);
  input gt_a, gt_b;
  output gt_out;
   wire temp;
  not n2(temp,gt_a);
  and a2(gt_out, temp, gt_b);
endmodule

module eq(eq_out, eq_a, eq_b);
  input eq_a, eq_b;
  output eq_out;
  xnor x1 (eq_out, eq_a, eq_b);
endmodule

 

Testbench:

module twoBitComapratorTB;
  reg [1:0] x,y;
  wire greater,less,equal;
  
  twoBitComparator DUT(.tbc_eq(equal),.tbc_lt(less),.tbc_gt(greater),.A(x),.B(y));
  
  initial
    begin
      #0 x=2'b00; y=2'b00;
      #10 x=2'b00; y=2'b01;
      #20 x=2'b00; y=2'b10;
      #30 x=2'b00; y=2'b11;
      #40 x=2'b01; y=2'b00;
      #50 x=2'b01; y=2'b01;
      #60 x=2'b01; y=2'b10;
      #70 x=2'b01; y=2'b11;
      #80 x=2'b10; y=2'b00;
      #90 x=2'b10; y=2'b01;
      #100 x=2'b10; y=2'b10;
      #110 x=2'b10; y=2'b11;
      #120 x=2'b11; y=2'b00;
      #130 x=2'b11; y=2'b01;
      #140 x=2'b11; y=2'b10;
      #150 x=2'b11; y=2'b11;
    end
  
  initial
    begin
      $monitor("X0X1 = %b%b, Y0Y1 = %b%b, Equal=%b, Less=%b, Greater=%b", x[1],x[0],y[1],y[0],equal,less,greater);
    end
  
initial
 begin
    $dumpfile("twoBitComapratorTB.vcd");
    $dumpvars(0,twoBitComapratorTB);
 end
endmodule

 

Output:

X0X1 = 00, Y0Y1 = 00, Equal=1, Less=0, Greater=0
X0X1 = 00, Y0Y1 = 01, Equal=0, Less=0, Greater=1
X0X1 = 00, Y0Y1 = 10, Equal=0, Less=0, Greater=1
X0X1 = 00, Y0Y1 = 11, Equal=0, Less=0, Greater=1
X0X1 = 01, Y0Y1 = 00, Equal=0, Less=1, Greater=0
X0X1 = 01, Y0Y1 = 01, Equal=1, Less=0, Greater=0
X0X1 = 01, Y0Y1 = 10, Equal=0, Less=0, Greater=1
X0X1 = 01, Y0Y1 = 11, Equal=0, Less=0, Greater=1
X0X1 = 10, Y0Y1 = 00, Equal=0, Less=1, Greater=0
X0X1 = 10, Y0Y1 = 01, Equal=0, Less=1, Greater=0
X0X1 = 10, Y0Y1 = 10, Equal=1, Less=0, Greater=0
X0X1 = 10, Y0Y1 = 11, Equal=0, Less=0, Greater=1
X0X1 = 11, Y0Y1 = 00, Equal=0, Less=1, Greater=0
X0X1 = 11, Y0Y1 = 01, Equal=0, Less=1, Greater=0
X0X1 = 11, Y0Y1 = 10, Equal=0, Less=1, Greater=0
X0X1 = 11, Y0Y1 = 11, Equal=1, Less=0, Greater=0

 

Simulation:

Comparator-Verilog-Testbench-Output

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