AND Logic Gate Modeling Using Verilog

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AND GATE CIRCUIT:

AND-GATE-CIRCUIT-DAIGRAM

TRUTH TABLE:

X Y Output(Z)
0 0 0
1 0 0
0 1 0
1 1 1

 

AND GATE MODELLING METHODS:

Data Flow Modelling:

`timescale 1ns / 1ps

module andGate(output z, input x,y);
  assign z=x&y; 
endmodule

 

Behavioral Modeling:

`timescale 1ns / 1ps

module andGate(output reg z, input x,y);
  always @ (x or y) 
    begin
      if (x == 1'b1 & y == 1'b1) 
        begin
          z = 1'b1;
        end
      else
        z = 1'b0;
    end
endmodule

 

Gate Level Modelling:

`timescale 1ns / 1ps

module andGate(output z, input x,y);
  and(z, x, y); 
endmodule

 

TESTBENCH:

`timescale 1ns / 1ps

module andGateTB();
  reg tx,ty;
  wire tz;
  
  andGate DUT(.z(tz),.x(tx),.y(ty));
  
  initial
    begin
         tx=0; ty=0;
      #2 tx=0; ty=1;
      #2 tx=1; ty=0;
      #2 tx=1; ty=1;
      #2 $finish;
    end
  
  initial
    begin
      $monitor ($time, " tx=%d, ty=%d, tz=%d",tx,ty,tz);
    end
  
  initial 
    begin
      $dumpfile("andGateTB.vcd"); 
      $dumpvars;
    end
  
endmodule

Output:

0 tx=0, ty=0, tz=0
2 tx=0, ty=1, tz=0
4 tx=1, ty=0, tz=0
6 tx=1, ty=1, tz=1

 

SIMULATION RESULTS:

And-Gate-Simulation-Output

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