Volatile Memory: SRAM and DRAM
Introduction Volatile memory is a type of computer memory that requires power to maintain stored information. When power is lost, the data stored in volatile memory is erased, distinguishing it …
verilog
4×1 Multiplexer Modeling Using Verilog With Testbench
Introduction A multiplexer (MUX) is a fundamental digital circuit that selects one of several input signals and forwards it to a single output line based on a set of select …
Second Complement With Testbench Using Verilog
Two(2’s) complement is a very basic concept of digital electronics where we just convert a given binary into a 2’s complement. There is a specific process to find 2’s complement …
Half Adder Modeling Using Verilog With Testbench
Introduction A half adder is a fundamental digital circuit used for adding two single-bit binary numbers, producing a sum and a carry output. It serves as a basic building block …
2×1 Multiplexer Design Using Verilog With Testbench
Introduction A multiplexer (MUX) is a fundamental digital circuit that selects one of several input signals and forwards it to a single output based on a control signal. A 2×1 …
Four Bit ALU Modeling Using Verilog With Testbench
Introduction An Arithmetic Logic Unit (ALU) is a critical component of a microprocessor, responsible for performing arithmetic and logical operations on binary data. A four-bit ALU, capable of processing four-bit …
NOR Logic Gate Modeling Using NAND Gates In Verilog
NOR GATE CIRCUIT USING NAND GATES: TRUTH TABLE: X Y Output(Z) 0 0 1 1 0 0 0 1 0 1 1 0 NOR GATE MODELING USING NAND GATES: …
XOR Logic Gate Modeling Using NAND Gates In Verilog
XOR GATE CIRCUIT USING NAND GATES: TRUTH TABLE: X Y Output(Z) 0 0 0 1 0 1 0 1 1 1 1 0 XOR GATE MODELING USING NAND GATES: …
NOT Logic Gate Modeling Using Verilog
NOT GATE CIRCUIT: TRUTH TABLE: X Output(Z) 0 1 1 0 XNOR GATE MODELLING METHODS: Data Flow Modelling: `timescale 1ns / 1ps module notGate(output z, input x); assign z= …
XNOR Logic Gate Modeling Using Verilog
XNOR GATE CIRCUIT: TRUTH TABLE: X Y Output(Z) 0 0 1 1 0 0 0 1 0 1 1 1 XNOR GATE MODELLING METHODS: Data Flow Modelling: `timescale 1ns …