RISC-V is an open-source instruction set architecture (ISA) that has garnered significant interest in academia and industry for its flexibility and adaptability. Developing and testing SystemVerilog RTL (Register Transfer Level) designs for RISC-V implementations requires robust test environments, particularly when focusing on open-source tools and testing the base ISA. In this article, we will explore a range of open-source RISC-V cores and testing environments, with a focus on using tools like Verilator for simulations. The aim is to provide practical guidance for testing RISC-V SystemVerilog RTL implementations.
A) Open-Source RISC-V Cores for Testing
Here is a curated list of RISC-V core implementations that offer potential for developing and testing SystemVerilog RTL designs:
1. Pulp Platform
- Repository: Pulp Platform GitHub
- Features:
- A robust platform with a variety of RISC-V cores.
- Comprehensive testing support, although details on testbenches require further exploration.
2. Shakti Processor
- Repository: Shakti Public Bitbucket
- Features:
- Open-source cores developed in India under the Shakti project.
- Provides SystemVerilog-based implementations.
3. PicoRV32
- Repository: PicoRV32 GitHub
- Features:
- A minimalistic RISC-V implementation optimized for FPGAs.
- Compact design with good Verilog compatibility.
4. RV12
- Repository: RV12 GitHub
- Features:
- Lightweight RISC-V implementation.
- Suitable for small embedded projects and easy integration.
5. SCR1
- Repository: SCR1 GitHub
- Features:
- High-performance RISC-V core.
- Open-source and suitable for extensive RTL testing.
6. E200 Open Source
- Repository: E200 GitHub
- Features:
- Compact and efficient RISC-V core.
- Focused on IoT and small-scale applications.
B) Test Environment Considerations
1. Simulation with Verilator
- Advantages:
- Verilator provides excellent support for SystemVerilog and is optimized for high-performance RTL simulation.
- It supports simulation of RTL code directly, though test logic must often be implemented in C++ or SystemC.
- Usage:
- Use Verilator to compile your SystemVerilog designs and write test scripts in C++.
- The ability to step through the simulation instruction-by-instruction allows detailed state verification.
2. Simulator with API Support
- Choosing a simulator with an API enables fine-grained control over the simulation process, allowing you to:
- Check internal states like General Purpose Registers (GPR), Program Counter (PC), and Control and Status Registers (CSR).
- Compare the simulation state against expected outputs.
C) Approach to Testing
1. Testbench Development
- A good testbench for RISC-V should include:
- Instruction Testing: Focus on verifying base ISA instructions.
- State Verification: Regular checks on the state of GPR, PC, and CSR during simulation.
- Error Injection: Simulate edge cases and erroneous inputs to validate robustness.
2. Writing Tests in C++ or SystemC
- Since Verilator does not support SystemVerilog testbenches natively, you can:
- Write test cases in C++ to interface with the compiled Verilog code.
- Use SystemC for more complex, system-level test scenarios.
3. Comparison Against ISA Simulator
- Use a trusted RISC-V ISA simulator to:
- Generate expected states for each instruction.
- Validate the RTL design step-by-step during simulation.
Conclusion
Testing RISC-V SystemVerilog RTL implementations is a challenging but rewarding task, particularly when leveraging open-source tools. Platforms like the Pulp Platform, PicoRV32, and Shakti processors offer excellent starting points for testing the base ISA. Tools like Verilator, with its high-performance simulation capabilities and SystemC/C++ support, make it feasible to build a detailed and effective test environment. By integrating an API-driven simulator and systematic testing methodologies, developers can ensure robust and accurate RTL designs while fully embracing the open-source nature of RISC-V.
For further exploration, the RISC-V Cores List provides a comprehensive overview of available implementations. Sharing progress and insights within the RISC-V community can also accelerate development and foster collaborative innovation.