Tasks and function concept is a little bit confusing in the Verilog language and both terms have a different purpose in Verilog. Let’s try to understand the difference and some similarities between them.
Tasks contain delays, timing, event constructs, or multiple output arguments. Function is used when common Verilog code is purely combinational, executes in zero simulation time and provides exactly one output.
They have some similarities like Function and task cannot have wire but both contain behavioral statements only. Now, look at the difference between them in detail that will give more clarity about it.
| Functions | Tasks |
|---|---|
| 1. A function always returns only one value | 1. A task cannot return any value but a similar concept can be done by using output arguments |
| 2. A function doesn’t have any inout, output arguments. | 2. A task has input, output arguments. |
| 3. At least one input argument is required. | 3. It may have zero or more arguments(input, output, inout). |
| 4. The function must not contain timing control statements, any delay and events. | 4. Tasks may contain timing control statements, any delay and event. |
| 5. A Function can enable another function but not another task. | 5. Tasks have the ability to enable other tasks and functions. |
| 6. A Function always execute in zero simulation time. | 6. Tasks may execute in non-zero simulation time. |