Four Bit Ripple Carry Adder Using Verilog With Testbench

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Introduction

A ripple carry adder (RCA) is a fundamental digital circuit used for adding binary numbers, forming the backbone of arithmetic operations in digital systems. A four-bit ripple carry adder performs addition on two four-bit binary numbers, producing a four-bit sum and a carry-out. This article explores the design and implementation of a four-bit ripple carry adder using Verilog, a hardware description language (HDL) widely utilized for modeling and verifying digital circuits.

The ripple carry adder is constructed by cascading four one-bit full adders, where each adder’s carry-out feeds into the next adder’s carry-in, creating a “ripple” effect. This tutorial provides a detailed guide to modeling the adder using Verilog’s structural modeling approach, including a comprehensive testbench to verify functionality and simulation results to confirm correctness. By understanding this design, readers can master essential concepts in digital arithmetic and Verilog programming.

Background

A ripple carry adder operates by adding two binary numbers bit by bit, starting from the least significant bit (LSB). Each bit addition is performed by a one-bit full adder, which takes three inputs: two operand bits (A and B) and a carry-in (Cin). The full adder produces a sum bit and a carry-out, which is passed to the next adder in the chain. For a four-bit RCA, four full adders are connected, with the final carry-out indicating overflow or carry for higher-order operations.

The operation of a one-bit full adder can be described by the following Boolean expressions:

Sum = A ⊕ B ⊕ Cin

Carry-out = (A ∧ B) ∨ (B ∧ Cin) ∨ (A ∧ Cin)

The ripple carry adder’s simplicity makes it an excellent educational tool, though its propagation delay (due to the carry rippling through each stage) can limit performance in larger designs. This article focuses on structural modeling, breaking the design into modular components for clarity and reusability.

Four-Bit Ripple Carry Adder Block Diagram

The block diagram of a four-bit ripple carry adder illustrates the cascading of four one-bit full adders. Each adder processes one bit of the inputs A and B, along with a carry-in, producing a sum bit and a carry-out that propagates to the next adder. The final carry-out (C4) indicates whether the addition results in an overflow.

4-Bit Ripple Carry Adder Block Diagram

Truth Table for One-Bit Full Adder

The truth table for a one-bit full adder defines the sum and carry-out for all possible input combinations of A, B, and Cin. This table is critical for understanding the building block of the four-bit RCA.

A B Cin Sum Carry-out
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1

Verilog Modeling of Four-Bit Ripple Carry Adder

The four-bit ripple carry adder is modeled using Verilog’s structural modeling approach, which emphasizes modularity by composing the design from smaller components. The design is broken into three modules: the main fourBitRippleCarryAdder module, the oneBitAdder module, and sub-modules for sum (sumModule) and carry (carryModule) calculations.

Main Module

The top-level module instantiates four one-bit full adders, connecting them in a ripple carry configuration. 

module fourBitRippleCarryAdder(s, c4, A, B, Cin);
    input [3:0] A, B;
    input Cin;
    output [3:0] s;
    wire [2:0] cout;
    output c4;
    oneBitAdder Add1 (s[0], cout[0], A[0], B[0], Cin);
    oneBitAdder Add2 (s[1], cout[1], A[1], B[1], cout[0]);
    oneBitAdder Add3 (s[2], cout[2], A[2], B[2], cout[1]);
    oneBitAdder Add4 (s[3], c4, A[3], B[3], cout[2]);
endmodule

The module takes two four-bit inputs (A and B), a carry-in (Cin), and produces a four-bit sum (s) and a final carry-out (c4). Intermediate carry signals (cout) connect the adders.

One-Bit Full Adder Module

The oneBitAdder module encapsulates the sum and carry logic for a single bit, using separate sub-modules for clarity. 

module oneBitAdder(s_out, c_out, l, m, n);
    input l, m, n;
    output s_out, c_out;
    sumModule s1 (s_out, l, m, n);
    carryModule c1 (c_out, l, m, n);
endmodule

Inputs l, m, and n represent the two operand bits and carry-in, respectively. The module instantiates sumModule and carryModule to compute the sum and carry-out.

Sum Module

The sumModule computes the sum bit using XOR operations, as per the full adder’s sum equation. 

module sumModule(sumOut, x, y, c_in);
    input x, y, c_in;
    output sumOut;
    wire t;
    xor x1 (t, x, y);
    xor x2 (sumOut, t, c_in);
endmodule

The sum is calculated as sumOut = x ⊕ y ⊕ c_in, using two XOR gates for efficiency.

Carry Module

The carryModule computes the carry-out using AND and OR gates, based on the carry equation. 

module carryModule(carr_out, A, B, Cin);
    output carr_out;
    input A, B, Cin;
    wire t1, t2, t3;
    and a1 (t1, A, B);
    and a2 (t2, B, Cin);
    and a3 (t3, A, Cin);
    or o1 (carr_out, t1, t2, t3);
endmodule

The carry-out is computed as carr_out = (A ∧ B) ∨ (B ∧ Cin) ∨ (A ∧ Cin), using three AND gates and one OR gate.

Note: The structural approach enhances modularity, making the design easier to understand and maintain. However, it may result in longer simulation times compared to behavioral modeling due to the explicit gate-level description.

Testbench for Verification

The testbench verifies the four-bit ripple carry adder by applying a variety of input combinations and monitoring the outputs. It tests different scenarios, including cases with and without carry-in, to ensure robust functionality. 

module fourBitRippleCarryAdderTb;
    reg [3:0] ta, tb;
    reg tc;
    wire [3:0] tsum;
    wire tcr;
    fourBitRippleCarryAdder DUT (.s(tsum), .c4(tcr), .A(ta), .B(tb), .Cin(tc));
    initial
    begin
        #0 ta=4'b0000; tb=4'b0000; tc=1'b1;
        #1 ta=4'b1110; tb=4'b0111; tc=1'b1;
        #2 ta=4'b0011; tb=4'b0111; tc=1'b1;
        #3 ta=4'b1100; tb=4'b1100; tc=1'b0;
        #4 ta=4'b0101; tb=4'b0101; tc=1'b1;
        #5 ta=4'b1101; tb=4'b0111; tc=1'b0;
        #6 ta=4'b0001; tb=4'b0011; tc=1'b1;
        #7 ta=4'b1111; tb=4'b1001; tc=1'b1;
        #8 ta=4'b1011; tb=4'b1110; tc=1'b0;
        #9 ta=4'b0011; tb=4'b1100; tc=1'b0;
    end
    initial
    begin
        $monitor($time, " ta=%d, tb=%d, tc=%d, tsum=%d, tcr=%d", ta, tb, tc, tsum, tcr);
    end
    initial
    begin
        $dumpfile("fourBitRippleCarryAdderTb.vcd");
        $dumpvars;
    end
endmodule

The testbench applies ten test cases, varying inputs ta (A), tb (B), and tc (Cin) over time, with delays to allow signal propagation. The $monitor statement logs the inputs, sum (tsum), and carry-out (tcr), while $dumpfile and $dumpvars generate a VCD file for waveform analysis.

Output:

00 ta= 0, tb= 0, tc=1, tsum= 1, tcr=0 // 0 + 0 + 1 = 1
01 ta=14, tb= 7, tc=1, tsum= 6, tcr=1 // 14 + 7 + 1 = 22 (sum=6, carry=1)
03 ta= 3, tb= 7, tc=1, tsum=11, tcr=0 // 3 + 7 + 1 = 11
06 ta=12, tb=12, tc=0, tsum= 8, tcr=1 // 12 + 12 = 24 (sum=8, carry=1)
10 ta= 5, tb= 5, tc=1, tsum=11, tcr=0 // 5 + 5 + 1 = 11
15 ta=13, tb= 7, tc=0, tsum= 4, tcr=1 // 13 + 7 = 20 (sum=4, carry=1)
21 ta= 1, tb= 3, tc=1, tsum= 5, tcr=0 // 1 + 3 + 1 = 5
28 ta=15, tb= 9, tc=1, tsum= 9, tcr=1 // 15 + 9 + 1 = 25 (sum=9, carry=1)
36 ta=11, tb=14, tc=0, tsum= 9, tcr=1 // 11 + 14 = 25 (sum=9, carry=1)
45 ta= 3, tb=12, tc=0, tsum=15, tcr=0 // 3 + 12 = 15

The output confirms the adder’s correctness, with sums and carry-outs matching expected results for each test case.

Simulation Results

The simulation waveform visualizes the testbench results, displaying the input signals (ta, tb, tc) and outputs (tsum, tcr) over time. This graphical representation is invaluable for verifying the adder’s behavior and debugging timing issues.

4-Bit Ripple Carry Adder Simulation Output

Applications of Ripple Carry Adders

Ripple carry adders are widely used in digital systems, including:

  • Arithmetic Logic Units (ALUs): Forming the addition component in microprocessor ALUs.
  • Microcontrollers: Enabling arithmetic operations in embedded systems.
  • Digital Signal Processing: Supporting addition in DSP algorithms for audio and image processing.
  • Educational Tools: Teaching binary arithmetic and digital design principles.
  • Simple Calculators: Performing basic arithmetic in low-power devices.

While simple and easy to implement, ripple carry adders are slower for large bit widths due to carry propagation delays. Advanced designs like carry-lookahead adders address this limitation for high-performance applications.

Enhancements and Considerations

The four-bit ripple carry adder design can be enhanced for practical applications:

  • Carry-Lookahead Logic: To reduce propagation delay by precomputing carry signals.
  • Overflow Detection: To flag when the sum exceeds the four-bit range.
  • Behavioral Modeling: Using a single expression like s = A + B + Cin for simplicity in larger designs.
  • Pipelining: To improve throughput in high-speed applications.

These enhancements can improve performance and functionality, making the adder suitable for more complex systems.

Conclusion

Modeling a four-bit ripple carry adder in Verilog demonstrates the power of structural modeling in creating modular, reusable digital designs. By breaking the adder into one-bit full adders and sub-modules for sum and carry calculations, the design achieves clarity and maintainability. The testbench and simulation results verify the adder’s functionality across various input scenarios, confirming its correctness. Mastering ripple carry adder design equips engineers with foundational skills for building arithmetic circuits, paving the way for advanced digital system development using Verilog.

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