Half Adder Modeling Using Verilog With Testbench

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HALF ADDER BLOCK DIAGRAM:

Half-Adder-Diagram-Design

 

TRUTH TABLE:

A B SUM CARRY
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

 

HALF ADDER GATE CIRCUIT DESIGN:

Half-Adder-Logic-Circuit-Design

 

HALF ADDER GATE MODELING:

`timescale 1ns / 1ps

module halfAdder (sum,carry,a,b);
  input a,b;
  output sum;
  output carry;
  
  assign sum = a^b;
  assign carry = a&b;
endmodule

 

TESTBENCH:

`timescale 1ns / 1ps

module halfAdderTB();
  reg ta,tb;
  wire tsum,tcarry;
  
  halfAdder DUT(.sum(tsum),.carry(tcarry),.a(ta),.b(tb));
  
  initial
    begin
      $monitor("time=%d, ta = %b, tb = %b, tsum = %b, tcarry = %b t",$time,ta,tb,tsum,tcarry);
      	  ta = 1'b0; tb = 1'b0; 
      #2; ta = 1'b0; tb = 1'b1;
      #2; ta = 1'b1; tb = 1'b0;
      #2; ta = 1'b1; tb = 1'b1; 
      #2; $finish;
    end
  
  initial 
    begin
      $dumpfile("halfAdderTB.vcd"); 
      $dumpvars;
    end
endmodule

Output:

time= 0, ta = 0, tb = 0, tsum = 0, tcarry = 0 	
time= 2, ta = 0, tb = 1, tsum = 1, tcarry = 0 	
time= 4, ta = 1, tb = 0, tsum = 1, tcarry = 0 	
time= 6, ta = 1, tb = 1, tsum = 0, tcarry = 1

 

SIMULATION RESULTS:

Half-Adder-Circuit-Simulation-Output

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