JK Flip Flop Design Using Verilog With Testbbench

What Is a JK Flip Flop?

A JK Flip Flop is a clocked sequential logic circuit that improves upon the SR Flip Flop by resolving its forbidden state. The name “JK” is attributed to Jack Kilby, the inventor of the integrated circuit. It has two data inputs — J (analogous to Set) and K (analogous to Reset) — along with a CLK (clock) input and an output Q.

Key characteristics of the JK Flip Flop include:

• No Forbidden State: Unlike SR Flip Flops, the condition J=1, K=1 is valid and causes the output to toggle.
• Clock-Controlled: State changes occur only on the active clock edge (typically positive/rising edge).
• Four Operating Modes: Memory (no change), Reset, Set, and Toggle — one for each input combination.
• Foundation for Counters: The toggle behavior makes JK Flip Flops the building block of binary counters and shift registers.

JK Flip Flops are widely used in digital electronics for frequency division, data storage, and synchronous counter design.

Block Diagram and Circuit Diagram

The block diagram of a JK Flip Flop shows the three inputs (J, K, CLK) and two complementary outputs (Q and Q’). The logic circuit is typically implemented using NAND gates built on top of an SR latch structure.

Block Diagram

Logic Circuit Diagram

The logic circuit of a JK Flip Flop uses NAND gates to feed back the Q and Q’ outputs to the inputs, preventing the indeterminate state that occurs in a basic SR Flip Flop.

Note: The feedback connections from Q and Q’ to the input NAND gates are what distinguish the JK Flip Flop from the SR Flip Flop and prevent undefined output.

Truth Table

The truth table of a JK Flip Flop describes the output Q for every combination of J, K, and CLK inputs. The symbol X denotes a “don’t care” condition, and Q’ represents the complement (toggle) of the current output.

Note: When the clock is LOW (0), the flip flop ignores J and K and retains its previous state regardless of input values.

Core Concepts of JK Flip Flop

The JK Flip Flop involves several key concepts essential for understanding its behavior and implementing it in digital systems. We’ll cover these in detail.

1. Operating Modes

The JK Flip Flop has four distinct operating modes based on the J and K input values when the clock pulse is active:

• Memory Mode (J=0, K=0): The output Q retains its previous value. No state change occurs.
• Reset Mode (J=0, K=1): The output Q is forced to 0 regardless of its current state.
• Set Mode (J=1, K=0): The output Q is forced to 1 regardless of its current state.
• Toggle Mode (J=1, K=1): The output Q flips to its complement. If Q was 1, it becomes 0, and vice versa.

2. Verilog Implementation

The JK Flip Flop can be modeled in Verilog using an always block triggered on the positive clock edge. The module takes J, K, and CLK as inputs and produces Q as a registered output.

module jkFlipFlop(J, K, CLK, Q);
  input J, K, CLK;
  output reg Q = 1;

  always @(posedge CLK, J or K or Q)
    begin
      if(J==0)
        begin
          if(K==0) Q = Q;   // Memory: no change
          if(K==1) Q = 0;   // Reset
        end

      if(J==1)
        begin
          if(K==0) Q = 1;   // Set
          if(K==1) Q = ~Q;  // Toggle
        end
    end

endmodule
        

Output:

0 CLK=0, J=x, K=x, Q=1
5 CLK=1, J=0, K=0, Q=1
7 CLK=1, J=0, K=1, Q=0
8 CLK=1, J=1, K=0, Q=1
9 CLK=1, J=1, K=1, Q=0
        

Note: The initial value of Q is set to 1 using output reg Q = 1. The always block is sensitive to the positive clock edge, J, K, and Q to capture all transitions correctly.

3. Writing the Testbench

A testbench is used to verify the behavior of the JK Flip Flop by applying stimulus (different J and K values) and monitoring the output Q. The testbench instantiates the DUT (Device Under Test) and generates a clock signal using an always block.

module jkFlipFlopTB;
  reg J, K, CLK = 1;
  wire Q;

  // Instantiate the DUT
  jkFlipFlop DUT(.J(J), .K(K), .CLK(CLK), .Q(Q));

  // Clock generation: toggles every 5 time units
  always
    begin
      CLK = !CLK;
      #5;
    end

  // Stimulus: apply different J, K combinations
  initial
    begin
      #5 J = 1'b0; K = 1'b0;  // Memory
      #2 J = 1'b0; K = 1'b1;  // Reset
      #1 J = 1'b1; K = 1'b0;  // Set
      #1 J = 1'b1; K = 1'b1;  // Toggle
      $finish;
    end

  // Monitor output at each change
  initial
    begin
      $monitor($time, " CLK=%b, J=%b, K=%b, Q=%b", CLK, J, K, Q);
    end

endmodule
        

Output:

0 CLK=0, J=x, K=x, Q=1
5 CLK=1, J=0, K=0, Q=1
7 CLK=1, J=0, K=1, Q=0
8 CLK=1, J=1, K=0, Q=1
9 CLK=1, J=1, K=1, Q=0
        

Note: The $monitor system task automatically prints the signal values whenever any of the monitored signals change. The $finish task ends the simulation after all stimulus is applied.

4. Characteristic Equation

The characteristic equation of a JK Flip Flop expresses the next state Q(t+1) in terms of the current state Q(t) and the inputs J and K:

• Q(t+1) = J·Q'(t) + K’·Q(t)
• When J=0, K=0: Q(t+1) = Q(t) — Memory
• When J=0, K=1: Q(t+1) = 0 — Reset
• When J=1, K=0: Q(t+1) = 1 — Set
• When J=1, K=1: Q(t+1) = Q'(t) — Toggle

This equation is used in the design of sequential circuits, including state machine synthesis and counter design.

5. JK Flip Flop vs SR Flip Flop

The JK Flip Flop directly improves upon the SR Flip Flop by handling the previously undefined S=1, R=1 case through the toggle operation.

6. Simulation Output Explained

Reading the simulation output step by step helps verify that the Verilog model is functioning correctly:

• Time 0: CLK=0, J and K are unknown (x), Q initializes to 1.
• Time 5: CLK rises to 1, J=0, K=0 → Memory mode, Q remains 1.
• Time 7: J=0, K=1 → Reset mode, Q becomes 0.
• Time 8: J=1, K=0 → Set mode, Q becomes 1.
• Time 9: J=1, K=1 → Toggle mode, Q flips from 1 to 0.

All four operating modes are verified successfully by the testbench simulation.

Why Is the JK Flip Flop Important?

The JK Flip Flop is one of the most important building blocks in digital logic design for the following reasons:

1. Eliminates Undefined States: Solves the forbidden state problem of the SR Flip Flop by defining the toggle behavior for J=1, K=1.
2. Counter Design: The toggle mode makes it ideal for designing binary ripple counters and synchronous counters.
3. Frequency Division: A JK Flip Flop in toggle mode divides the clock frequency by 2, useful in digital clocks and timers.
4. Shift Registers: Used in serial-to-parallel and parallel-to-serial data converters.
5. State Machines: Commonly used as the memory element in Mealy and Moore finite state machines.

Tips for Using JK Flip Flops

• Use Posedge Triggering: Always specify whether the flip flop triggers on posedge or negedge of CLK to avoid ambiguous simulation behavior.
• Initialize Output Register: Assign an initial value to Q in the port declaration (e.g., output reg Q = 0) to avoid unknown states at simulation start.
• Avoid Combinational Feedback: Do not feed Q directly into J or K in a combinational path without proper clock gating — this can cause oscillations.
• Use Non-Blocking Assignments for Sequential Logic: In real RTL design, prefer <= (non-blocking) over = (blocking) inside always @(posedge CLK) blocks to avoid race conditions.
• Verify with Testbench: Always simulate all four input combinations (00, 01, 10, 11) to confirm correct Set, Reset, Memory, and Toggle behavior.
• Understand the Characteristic Equation: Use Q(t+1) = J·Q’ + K’·Q when synthesizing or converting to other flip flop types during state machine design.

Example: Using JK Flip Flop in a Program

The following is a complete, well-commented Verilog implementation of the JK Flip Flop along with its testbench, demonstrating all four operating modes in a single simulation run.

// ============================================
// JK Flip Flop - Verilog RTL Implementation
// ============================================
module jkFlipFlop(J, K, CLK, Q);
  input J, K, CLK;
  output reg Q = 1;  // Initialize Q to 1

  // Trigger on positive clock edge
  always @(posedge CLK, J or K or Q)
    begin
      if(J==0)
        begin
          if(K==0) Q = Q;   // Memory: retain current state
          if(K==1) Q = 0;   // Reset: force output to 0
        end
      if(J==1)
        begin
          if(K==0) Q = 1;   // Set: force output to 1
          if(K==1) Q = ~Q;  // Toggle: invert current output
        end
    end

endmodule

// ============================================
// JK Flip Flop Testbench
// ============================================
module jkFlipFlopTB;
  reg J, K, CLK = 1;
  wire Q;

  // Instantiate Device Under Test (DUT)
  jkFlipFlop DUT(.J(J), .K(K), .CLK(CLK), .Q(Q));

  // Clock: period = 10 time units (toggle every 5)
  always
    begin
      CLK = !CLK;
      #5;
    end

  // Apply stimulus for all 4 JK combinations
  initial
    begin
      #5 J = 1'b0; K = 1'b0;  // Test Memory mode
      #2 J = 1'b0; K = 1'b1;  // Test Reset mode
      #1 J = 1'b1; K = 1'b0;  // Test Set mode
      #1 J = 1'b1; K = 1'b1;  // Test Toggle mode
      $finish;
    end

  // Monitor and display output
  initial
    begin
      $monitor($time, " CLK=%b, J=%b, K=%b, Q=%b", CLK, J, K, Q);
    end

endmodule
        

Output:

0 CLK=0, J=x, K=x, Q=1
5 CLK=1, J=0, K=0, Q=1
7 CLK=1, J=0, K=1, Q=0
8 CLK=1, J=1, K=0, Q=1
9 CLK=1, J=1, K=1, Q=0
        

This complete example demonstrates all four operating modes of the JK Flip Flop — Memory, Reset, Set, and Toggle — verified through a structured testbench with clock generation and $monitor for real-time output tracking.

Did You Know?

• The JK Flip Flop is named in honor of Jack Kilby, the Nobel Prize-winning engineer who invented the integrated circuit in 1958 at Texas Instruments.
• A single JK Flip Flop wired in toggle mode (J=1, K=1 always) acts as a divide-by-2 frequency divider — the foundation of binary counters used in CPUs and digital clocks.
• JK Flip Flops can be used to build D Flip Flops and T Flip Flops by simply tying their inputs together or to fixed logic levels, making them the most versatile of all flip flop types.
• In FPGAs, the underlying storage element is typically a D Flip Flop, but synthesis tools automatically convert JK Flip Flop logic into equivalent D-based implementations.