Multiplexer Design Using Verilog With Testbench

`timescale 1ns / 1ps

module MuxDesign2x1(A,B,select,Y);
  input select,A,B;
  output Y;
  wire output1,output2,selectbar;
  
  not (selectbar,select);
  and (output1,selectbar,A);
  and (output2,select,B);
  or (Y,output1,output2);
endmodule

`timescale 1ns / 1ps

module MuxDesign2x1TB();
  reg tA,tB,tselect;
  wire tY;
  
  MuxDesign2x1 DUT(.A(tA),.B(tB),.select(tselect),.Y(tY));
  initial
    begin
      	 tA=0; tB=1; tselect=0;
      #2 tA=1; tB=0; tselect=0;
      #2 tA=1; tB=0; tselect=1;
      #2 tA=0; tB=1; tselect=1;
      #2 $finish;
    end
  
   initial
    begin
      $monitor (,$time,", tA=%d, tB=%d, select=%d, tY=%d",tA,tB,tselect,tY,);
    end
  
  initial 
    begin
      $dumpfile("MuxDesign2x1TB.vcd"); 
      $dumpvars;
    end
endmodule

0, tA=0, tB=1, select=0, tY=0 
2, tA=1, tB=0, select=0, tY=1 
4, tA=1, tB=0, select=1, tY=0 
6, tA=0, tB=1, select=1, tY=1