NOR Logic Gate Modeling Using NAND Gates In Verilog

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NOR GATE CIRCUIT USING NAND GATES:

NOR-CIRCUIT-DIAGRAM-GATE-USING-NAND

TRUTH TABLE:

X Y Output(Z)
0 0 1
1 0 0
0 1 0
1 1 0

 

NOR GATE MODELING USING NAND GATES:

`timescale 1ns / 1ps

module norUsingNand(output z, input x,y);
  wire w1,w2,w3;
  
  nand (w1,x,x);
  nand (w2,y,y);
  nand (w3,w2,w1);
  nand (z,w3,w3);
endmodule

 

TESTBENCH:

`timescale 1ns / 1ps

module norUsingNandTB();
  reg tx,ty;
  wire tz;
  
  norUsingNand DUT(.z(tz),.x(tx),.y(ty));
  initial
    begin
      	 tx=0;ty=0;
      #2 tx=0;ty=1;
      #2 tx=1;ty=0;
      #2 tx=1;ty=1;
      #2 $finish;
    end
  
   initial
    begin
      $monitor ($time, " tx=%d, ty=%d, tz=%d",tx,ty,tz);
    end
  
  initial 
    begin
      $dumpfile("norUsingNandTB.vcd"); 
      $dumpvars;
    end
endmodule

Output:

0 tx=0, ty=0, tz=1
2 tx=0, ty=1, tz=0
4 tx=1, ty=0, tz=0
6 tx=1, ty=1, tz=0

 

SIMULATION RESULTS:

Nor-Gate-Using-Nand-Simulation-Output

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