OR Logic Gate Modeling Using Verilog

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In this tutorial, we are going to design “OR Logic Gate” using Verilog. There are different design methods to model digital circuits in Verilog like gate level, data flow, and behavioral modeling. We will cover all those methods one by one with testbench and simulation results.

OR GATE CIRCUIT:

OR-GATE-CIRCUIT-DIAGRAM

TRUTH TABLE:

X Y Output(Z)
0 0 0
1 0 1
0 1 1
1 1 1

 

OR GATE MODELLING METHODS:

Data Flow Modelling:

`timescale 1ns / 1ps

module orGate(output z, input x,y);
  assign z=x|y; 
endmodule

 

Behavioral Modeling:

`timescale 1ns / 1ps

module orGate(output reg z, input x,y);
  always @ (x or y) 
    begin
      if (x == 1'b0 & y == 1'b0) 
        begin
          z = 1'b0;
        end
      else
        z = 1'b1;
    end
endmodule

 

Gate Level Modelling:

`timescale 1ns / 1ps

module orGate(output z, input x,y);
  or(z, x, y); 
endmodule

 

TESTBENCH:

`timescale 1ns / 1ps

module orGateTB();
  reg tx,ty;
  wire tz;
  
  orGate DUT(.z(tz),.x(tx),.y(ty));
  
  initial
    begin
         tx=0; ty=0;
      #2 tx=0; ty=1;
      #2 tx=1; ty=0;
      #2 tx=1; ty=1;
      #2 $finish;
    end
  
  initial
    begin
      $monitor ($time, " tx=%d, ty=%d, tz=%d",tx,ty,tz);
    end
  
  initial 
    begin
      $dumpfile("orGateTB.vcd"); 
      $dumpvars;
    end
  
endmodule

Output:

0 tx=0, ty=0, tz=0
2 tx=0, ty=1, tz=1
4 tx=1, ty=0, tz=1
6 tx=1, ty=1, tz=1

 

SIMULATION RESULTS:

Or-Gate-Simulation-Output

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