Physical Design Cycle In VLSI

1. Physical Design Cycle:

The input to the physical design cycle is a circuit diagram and the output is the layout of the circuit.

Figure: Physical Design Cycle

1.1 Partitioning:

A chip may contain several million transistors.

• Due to the limitations of memory space and computation power available it may not be possible to layout the entire chip (or generically speaking any large circuit) in the same step.
• Therefore, the chip (circuit) is normally partitioned into sub-chips (sub-circuits) called blocks.
• Partitioning process considers many factors such as the size of the blocks, number of blocks, and number of interconnections between the blocks.
• The output of partitioning is a set of blocks and the interconnections required between blocks.
• In large circuits, the partitioning process is hierarchical
• Each top block is then partitioned recursively into smaller blocks.

1.2 Floorplanning and Placement:

• This step is concerned with selecting good layout alternatives for each block, as well as the entire chip.
• The area of each block can be estimated after partitioning and is based approximately on the number and the type of components in that block.
• In addition, interconnect area required within the block must be considered.
• The actual rectangular shape of the block, which is determined by the aspect ratio may, however, be varied within a pre-specified range.
• Floorplanning is a critical step, as it sets up the ground work for a good layout. However, it is computationally quite hard.
• Very often the task of floorplanning is done by a design engineer, rather than a CAD tool. This is due to the fact that a human is better at ‘visualizing’ the entire floorplan and taking into account the information flow.
• Manual floorplanning is sometimes necessary as the major components of an IC need to be placed in accordance with the signal flow of the chip.
• In addition, certain components are often required to be located at specific positions on the chip.
• During placement, the blocks are exactly positioned on the chip.
• The goal of placement is to find a minimum area arrangement for the blocks that allows completion of interconnections between the blocks, while meeting the performance constraints.
• Avoid a placement which is routable but does not allow certain nets to meet their timing goals.
• Typically done in two phases.
• In the first phase an initial placement is created.
• In the second phase, the initial placement is evaluated and iterative improvements are made until the layout has minimum area or best performance and conforms to design specifications.
• The quality of the placement will not be evident until the routing phase has been completed
• Placement may lead to an unroutable design, i.e., routing may not be possible in the space provided. In that case, another iteration of placement is necessary.
• Good routing and circuit performance depend heavily on a good placement algorithm.
• Late placement changes lead to increased die size and lower quality designs.

1.3 Routing:

The objective of the routing phase is to complete the interconnections between blocks according to the specified netlist.

• First, the space not occupied by the blocks (called the routing space) is partitioned into rectangular regions called channels and switchboxes.
• This includes the space between the blocks as well the as the space on top of the blocks.
• The goal of a router is to complete all circuit connections using the shortest possible wire length and using only the channel and switch boxes.
• This is usually done in two phases:
  1. Global Routing Phase
  2. Detailed Routing phase
• • Global Routing: Connections are completed between the proper blocks of the circuit disregarding the exact geometric details of each wire and pin. For each wire, the global router finds a list of channels and switchboxes which are to be used as a passageway for that wire. In other words, global routing specifies the different regions in the routing space through which a wire should be routed. Global routing is followed by detailed routing.
  • Detailed Routing: It completes point-to-point connections between pins on the blocks.
• Global routing is converted into exact routing by specifying geometric information such as the location and spacing of wires and their layer assignments.
• Detailed routing includes channel routing and switchbox routing, and is done for each channel and switchbox.

Figure: Global And Detailed Routing

1.4 Compaction:

Compaction is simply the task of compressing the layout in all directions such that the total area is reduced.

• By making the chip smaller, wire lengths are reduced, which in turn reduces the signal delay between components of the circuit.
• At the same time, a smaller area may imply more chips can be produced on a wafer, which in turn reduces the cost of manufacturing.
• However, the expense of computing time mandates that extensive compaction is used only for large volume applications, such as microprocessors.
• Compaction must ensure that no rules regarding the design and fabrication process are violated during the process.

1.5 Extraction and Verification:

• Design Rule Checking (DRC) is a process which verifies that all geometric patterns meet the design rules imposed by the fabrication process.
• The fabrication process requires a specific separation (in microns) between two adjacent wires. DRC must check such separation for millions of wires on the chip.
• After checking the layout for design rule violations and removing the design rule violations, the functionality of the layout is verified by Circuit Extraction.
• This is a reverse engineering process, and generates the circuit representation from the layout. The extracted description is compared with the circuit description to verify its correctness. This process is called Layout Versus Schematics (LVS) verification.
• Geometric information is extracted to compute Resistance and Capacitance. This allows accurate calculation of the timing of each component, including interconnect. This process is called Performance Verification.
• The extracted information is also used to check the reliability aspects of the layout. This process is called Reliability Verification and it ensures that layout will not fail due to electro-migration, self-heat and other effects.

Interview:

1. DEFT Semiconductor Interview Questions For DFT Profile
2. Cerium Systems Interview Questions For Verification Profile

• Physical design, like VLSI design, is iterative in nature and many steps, such as global routing and channel routing, are repeated several times to obtain a better layout.
• the quality of results obtained in a step depends on the quality of the solution obtained in earlier steps.
• partitioning, floor planning, and placement problems play a more important role in determining the area and chip performance, as compared to routing and compaction.
• In general, the whole design cycle may be repeated several times to accomplish the design objectives.

2. Physical Design Cycle After New Trends:

Figure: Physical Design Cycle After New Trends

2.1 New Trends in Physical Design:

• As fabrication technology improves and process enters the deep sub-micron range, it is clear that interconnect delay is not scaling at the same rate as the gate delay. Therefore, interconnect delay is a more significant part of overall delay.
• As a result, in high performance chips, interconnect delay must be considered from very early design stages. In order to reduce interconnect delay several methods can be employed.
• Chip level signal planning: At the chip level, routing of major signals and buses must be planned from early design stages, so that interconnect distances can be minimized.
• In addition, these global signals must be routed in the top metal layers, which have low delay per unit length.
• OTC routing: Over-the-Cell (OTC) routing is a term used to describe routing over blocks and active areas.
• This is a departure from conventional channel and switchbox routing approach. Actually, chip level signal planning is OTC routing on the entire chip.
• The OTC approach can also be used within a block to reduce area and improve performance.
• The OTC routing approach essentially makes routing a three dimensional problem.
• Another effect of the OTC routing approach is that the pins are not brought to the block boundaries for connections to other blocks.
• Instead, pins are brought to the top of the block as a sea-of-pins. This concept, technically called the Arbitrary Terminal Model (ATM).

2.2 Cells Design Style:

• market requirements demand, quick time-to-market and high yield.
• As a result, restricted models and design styles are used in order to reduce the complexity of physical design Full-custom or semi-custom.
• In a full-custom layout, different blocks of a circuit can be placed at any location on a silicon wafer as long as all the blocks are non-overlapping.
• On the other hand, in semi-custom layout, some parts of a circuit are predesigned and placed on some specific place on the silicon wafer.
• Selection of a layout style depends on many factors including the type of chip, cost, and time-to-market.
• Full-custom layout is a preferred style for mass produced chips, since the time required to produce a highly optimized layout can be justified.
• On the other hand, to design an Application Specific Integrated Circuit (ASIC), a semi-custom layout style is usually preferred. On a large chip, each block may use a different layout design style.

3. EDA Tools For Physical Design:

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