Second Complement With Testbench Using Verilog

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Two(2’s) complement is a very basic concept of digital electronics where we just convert a given binary into a 2’s complement. There is a specific process to find 2’s complement but here we are going to implement that digital electronics concept through Verilog, Which is very useful from a digital circuit design perspective. But let’s try to understand the process to convert simple binary into two’s complements.

 

 

 

Two’s Complement Concept:

Step-By-Step-Process-To-Finding-Twos-Complement

 

 

Verilog Code:

module secondComplement(Yout, Number);
  input[5:0] Number;
  output [5:0] Yout;
  wire [5:0] t1;
  firstComplement FC(t1, Number);
  assign Yout = t1 + 1'b1;
endmodule

module firstComplement(Y0, Number);
  input[5:0] Number;
  output [5:0] Y0;
  assign Y0 = ~Number;
endmodule

Testbench:

module secondComplementTB;
  reg[5:0] Num, Y;
  
  secondComplement DUT(.Yout(Y), .Number(Num));
  
  initial
    begin
      #0 Num=6'b111111;
      #10 Num=6'b11010;
      #20 Num=6'b100011;
      #30 Num=6'b111100;
    end
  
  initial
    begin
      $monitor("input=%b, SecondComplement=%b", Num, Y);
    end
endmodule

Output:

input=111111, SecondComplement=000001
input=011010, SecondComplement=100110
input=100011, SecondComplement=011101
input=111100, SecondComplement=000100

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